1. Field of the Invention
The invention relates to a disk drive device and a method for controlling the disk drive device for performing an improved write cache operation, and relates to a memory device and a method for controlling the memory device for performing the improved write cache operation.
2. Description of Related Art
In a hard disk drive device connected to a host processor through an interface, a write cache scheme has been used to save a processing time of the host processor. Describing the write cache scheme, when the hard-disk drive device is powered on, a main control circuit or MPU of the hard disk drive device enters into a POR (Power On Reset) status, and then enters into an initializing status in which many preparations for a read/write operation are made, e.g., a switching of a "write cache" status to an enable status. This status is called "write cache enable".
An operation of the MPU in the write cache enable status is represented by a block 1 shown in FIG. 1, in which the MPU waits for a write command and data sent from the host processor, and when the write command and data are received, the MPU stores the data in a cache memory, as shown in a block 2 in FIG. 1. The MPU then sends a write completion signal to the host processor through the interface, as shown in a block 3. The operation proceeds to a block 4, in which the MPU writes the data cached in the cache memory into the rotating data recording disk, such as a magnetic recording disk. The operation proceeds to an end block 5 to terminate the write cache operation. As described above, the MPU sends the write completion signal to the host processor before actually storing the data in the rotating data recording disk, so that the processing time of the host processor is saved.
Japanese patent application JP-A-8-77728 discloses a write cache scheme of a disk drive device connected to a host processor in which each time the disk drive device receives a write command from the host processor, a determination is made as to whether the write cache operation should be made. To this end, each time the write command is received, a cache monitor circuit monitors various parameters to determine as to whether the write cache mode should be turned ON or OFF. The parameters monitored by the cache monitor circuit are an error rate of an error correction circuit, an error rate at a verifying operation, a probability of occurrence of servo errors, etc. Japanese patent application JP-A-8-77728 is directed to control only the switching of the write cache mode ON or OFF, and does not discloses a control of a queue depth of the present invention.
A problem of the write cache scheme of the patent application JP-A-8-77728 is that the cache monitor circuit monitors the above various parameters to determine as to whether the write cache mode should be turned ON or OFF, each time the write command is sent from the host processor. It means that a command overhead is increased, and a write cache completion signal is sent to the host processor after a delay which is required to perform the operation of the cache monitor circuit, so that the processing time of the host processor is wasted.
It can be seen then that there is a need for a cache and method for caching that does not increase overhead or delays.